1. Technical Field
The present invention relates to the field of microprocessors, and in particular, to low power register files for use in microprocessors.
2. Background Art
Modern processors typically include extensive execution resources to support concurrent processing of multiple instructions. These execution resources receive data from a hierarchy of storage structures with varying access latencies. One or more register files are located on the processor chip to provide data to the execution resources with very low latencies. Other storage structure include on-chip caches, off-chip caches, and a main memory, which provide data to execution resources with correspondingly longer latencies. Because register files are a primary source of data for execution resources, high performance processors typically employ larger register files, which have more register entries and multiple read/write ports. These larger register files maintain more data near the processor""s execution resources, where it can be accessed with relatively low latency by multiple execution units.
Multi-ported register files can create significant power demands on the processor. This is especially true when the register file is implemented in domino logic, which provides greater speed and lower loading than static logic in return for greater power dissipation. However, some of this power dissipation is unnecessary. For example, a register file provides data from the register entries indicated at its read ports on each cycle of the processor""s clock. The register entries are indicated by voltage levels on each read port""s address lines. When a read port is in use, these voltage levels represent a valid register identifier (ID) specified by an instruction in an associated execution unit. If the read port is not in use, i.e. if no instruction is driving a valid register ID to the port, the voltage levels on the read port""s address lines typically retain their values from the previous access. Even though these values represent a no-longer-valid address, they cause data to be read out of a corresponding register entry, unless the read port is disabled.
The power consumed by these unnecessary reads can be significant, particularly for domino logic. Each bit of the register entry is represented by a storage node, which is in one of two voltage states according to whether the bit is a logic one or a logic zero. When the register entry is read, every storage node that represents a logic one discharges an associated domino node, which must be recharged for the next clock cycle. The power dissipated by discharging and recharging the domino node capacitances associated with no-longer-valid addresses is wasted. Register files based on static logic dissipate less power per read, but static logic is not typically suitable for large register files.
Similar power dissipation occurs on unused register file write ports. If unused write ports are not disabled, their logic gates change state (xe2x80x9ctogglexe2x80x9d) with the processor clock, consuming additional power. In addition, toggling an unused write port increases the chances that the register entry associated with the no-longer-valid address voltages will be updated improperly.
Some register files disable unused read/write ports by ANDing the clock signal that drives the storage nodes with an enable signal, e.g. an address-valid bit. Other register files use a similar enable signal to qualify the word-lines associated with the storage nodes. In both cases, the enable signal is loaded by each entry in the register file. Since register file accesses are typically on a speed path in the processor, any increase in signal loading reduces the speed at which signals can be switched.
The present invention addresses these and other problems associated with power consumption by register files.
The present invention provides a mechanism for reducing power consumption by register files. A reference value is stored in a selected entry of the register file, and the address of the selected entry is driven to the address decoder of a register port whenever the port is not used. The reference value is chosen so that the voltage nodes associated with its component bits are not discharged when the value is read.
A register file in accordance with the present invention includes a word-line for each register file entry. An address decoder selects a word-line indicated by a received address, and a word line driver applies a voltage to the selected word-line. A power-control module drives a selected address to the decoder in response to a power-down signal.
For one embodiment of the invention, a selected register file entry is assigned a value of zero, and the power-control module drives the address of the selected register file entry to the address decoder in response to a power-down signal.